Karan Shah

1

votes
1

answer
181

views

How to Separate Existing Project using Micro Service Architecture?

I have created one project in asp.net MVC for banking sector. At the time of development,We did not think about scaling.So we did not used any kind of modular architecture. But now I am facing lots of problem regarding deployment and development of new feature. If I develop any new feature then curr...
Karan Shah
1

votes
0

answer
51

views

Google Cloud project environment variable not set using Java snippet

I am trying to set up the environment variable for a Google Cloud project. I'm doing it in right way. But, Issue: Program runs without any error but the environment variable does not set after execution of program. Code: ProcessBuilder pb = new ProcessBuilder('export GOOGLE_CLOUD_PROJECT=elysiot-21...
karan shah
1

votes
1

answer
39

views

How to keep shape's position parameters in order to keep it's left-most side at given parameter “left”,but not mid point?

While using python-pptx module, I came to know it places shape determining shape's center at given length in left parameter. Suppose I have given shape = slide.shapes.add_textbox(Inches(1), top, width, height) then shape's center point will be placed 1 inches away from left side. What I want to do i...
Karan Shah
1

votes
1

answer
1.2k

views

VHDL error related to concatenation of variable

I am writing VHDL code in which I have used tempx and tempz as variables and tried to concatenate them, but I am having some errors on the line annotated below. Suggestions on what to do please? The errors are: Error (10500): VHDL syntax error at ArrayDivider.vhd(53) near text ':='; expecting '(',...
Karan Shah
1

votes
1

answer
1.5k

views

Option & type_option in System Verilog

Coveegroup x; C: Coverpoint a {type_option.weight=0;} Endgroup I want to set coverpoint C weight to 0, for all the instances of covergroup x. So I have used type_option, as option is for instance specific settings. I have created 4 objects of this covergroup, but in each object, C is considered for...
Karan Shah
1

votes
2

answer
1.5k

views

Syntax for looping through lower dimension of multidimensional associative array in a constraint

class ns_data_struct; rand bit [63:0] ns_size = 64'h0000_0000_0000_0800; endclass : ns_data_struct class conf; ns_data_struct ns_data[]; function new(); ns_data = new[5]; foreach (ns_data[i]) ns_data[i] = new(); endfunction endclass : conf class x; randc bit [63:0] slba; randc bit [63:0] nlb; bit [6...
Karan Shah
1

votes
1

answer
567

views

Unexpected Nonexistent Associative Array Warning in Questa after rollover

Normally in Associative Array, Rollover issue is taken care by the tool. But in QuestaSIM, I am facing the issue, like if key of the Associative Array is 64 bit variable, then after overflow, it does not store data properly. Suppose index is 65'h1_0000_0000_0000_0002, then ideally it should store th...
Karan Shah
1

votes
3

answer
687

views

How to reuse multiple always blocks in Verilog

Below is the always block code. I need to have same code 11 times, with same functionality but on different variables. So how can I reuse the code? always @(posedge tconClk or negedge tconRst_n) begin if(~tconRst_n) begin pulse_cnt
Karan Shah
1

votes
1

answer
93

views

Docker logs: npm self signed certificate error

I am trying to Install Hyperledger composer on Mac OS by using this tutorial. When I run the following command from tutorial composer network start --networkName tutorial-network --networkVersion 0.0.1 --networkAdmin admin --networkAdminEnrollSecret adminpw --card [email protected] --file networkad...
KARAN SHAH
1

votes
2

answer
816

views

Jhipster gateway Full authentication is required to access this resource

Hello all i am working on Jhipster on ubuntu os. my project set up was done sucessfully. but when trying to test apis it gives me error of authentication. here is the error occurred while testing API. it will be pleasure if someone help me out. Error: rExceptionResolver : Resolved exception caused b...
karan shah
1

votes
1

answer
2.3k

views

getting Webhook response error (206) when trying to give response Dynamically using webhook On Dialogflow

I am trying to make a google actions using DialogFlow api in java. I am using Webhook for request Response for actions on DialogFlow Shown in below image. when Trying This Code it works fine and gives proper response as dialogflow have predefined actions facility. Code: @PostMapping('/webhook') pub...
karan shah
1

votes
1

answer
2.8k

views

Visual C++ Debugging Error - wuser32.pdb not loaded

I have made a form (GUI) in Visual C++ & while debugging it step by step, I got the following error, which stopped further debugging of the code. The screenshot of the error is shown below. How to solve this?
Karan Shah
1

votes
2

answer
1.1k

views

Is there any method to know whether a member is declared random or not in a class in SV

// Current Class class x; rand int a; int b; // b is nonrandom as of now function new(); endfunction function abc; // if a != ref.a, where ref is reference object of class x, declared somewhere else a.rand_mode(0); endfunciton // Future Possible Class class x; rand int a; rand int b; // b is also a...
Karan Shah
1

votes
1

answer
334

views

Wait for A Bit Change in Same Timestep in SV

Here is the code module m; bit x; initial begin fork begin wait(x == 1); wait(x == 0); end begin @(x == 1); @(x == 0); end #10 $display('Timeout'); join_any disable fork; end initial begin #5; x = 1; // Some other Logical Stuff x = 0;; end endmodule Now in this code, Timeout will happen, becaus...
Karan Shah
1

votes
1

answer
3k

views

Parsing XML file using Logstash

I am trying to parse an XML file in Logstash. I want to use XPath to do the parsing of documents in XML. So when I run my config file the data loads into elasticsearch but It is not in the way I want to load the data. The data loaded in elasticsearch is each line in xml document Structure of my XML...
KARAN SHAH
5

votes
0

answer
21

views

How does it send slight different emails to multiple recipients, though having them in common 'to' section?

So I was trying mixmax - the chrome extension and got to know it tracks email open event even though the same mail is sent to multiple recipients and it is able to identify receivers properly. I checked and found that it adds different pixel URLs for all receivers, mail looks same (that's not my con...
Karan Shah
1

votes
2

answer
4k

views

What is need of Assign/Deassign in Verilog?

I am here giving here 2 Verilog modules, which during simulation behaves same. But I don't understand that why to use assign/deassign in these modules, i.e. what is the difference between these 2 codes? // Code 1 - Without assign-deassign module dff (q,qbar,clk,reset,d) input clk, reset, d; output r...
Karan Shah
3

votes
1

answer
1.3k

views

Cannot access page on Refresh due to Hasbangs in a React SPA

I'm using a ReactJS SPA created from https://github.com/facebookincubator/create-react-app I'm using S3 and Cloudfront to serve my website. Everything works fine until I reload the page - it throws an error (Access denied in my case) as it is not able to handle without the Hashbang. Note: It works f...
Karan Shah
1

votes
2

answer
4.9k

views

Vhdl Type mismatch error

I am having a type mismatch error, but all values are of same type std_logic. Here is the code Nx, Ny - generics ipx - an input port vector tempx, tempz - signals ipx : in std_logic_vector(Nx-1 downto 0); ....... signal tempx : std_logic_vector(Ny-1 downto 0) := ipx(Nx-1 downto Nx-Ny); (Signal init...
Karan Shah
2

votes
1

answer
791

views

About sequential code in FPGAs

In VHDL, in a process all steps will be executed sequentially, but I wonder how an FPGA can execute steps sequentially. I am very confused about how sequential assignments, functions and similar are being generated in an FPGA, so can anyone throw some light on this topic? process(d, clk) begin...
Karan Shah
3

votes
1

answer
2k

views

Usage of Clocking Blocks in Systemverilog

What is the exact usage of Clocking Blocks in System Verilog, and how does it differ from normal always @ (posedge clk) block? Some differences, which I know : Clocking Block samples input data from Preponed Region, whereas in normal always block, there are always chances of race condition. Clock...
Karan Shah
1

votes
1

answer
1.9k

views

ATMEGA32 UART Communication

I am trying to do serial communication in ATMEGA32 and I have a question: In asynchronous serial communication both UBRRH and UCSRC registers have same location. I don't know which conditions that location will act as UBRRH and for which conditions, it will act as UCSRC. I need different values for...
Karan Shah
2

votes
1

answer
98

views

What is the meaning of an object of the class inside it's class-endclass definition?

What is the meaning of the following code (2nd line) in which inside class uvm_resource_pool definition, instance (object) rp is created? class uvm_resource_pool; static local uvm_resource_pool rp = get(); // Function: get // // Returns the singleton handle to the resource pool static function uvm_r...
Karan Shah
1

votes
1

answer
1.9k

views

Regex in SV or UVM

What functions do I need to call to use Regular Expressions in Systemverilog/UVM? Note: I'm not asking how to use regular expressions, just method names.
Karan Shah
5

votes
4

answer
3.4k

views

Garbage character displayed while printing web fonts from Google Chrome

I have a problem with printing web fonts from Google chrome v 18 but it works totally fine with IE and Firefox, I am using CSS file to pass the web fonts and the code for it is as follows. @font-face { font-family: 'C39P24DmTtNormal'; src: url('WebFonts/v100025_-webfont.eot'); src: url('WebFonts/v10...
Karan Shah
2

votes
3

answer
3.4k

views

IllegalArgumentException: A ServletContext is required

Can't get my spring boot application running on AWS instance.It works fine on my machine but it looks like autowiring resolves correctly in one environment but not in another.Looks like I need to clean up configuration classes a bit.Any ideas here? Thanks much. **Main class:** @Configuration @Enable...
Karan Shah
3

votes
2

answer
60

views

How do we use 'and' operator in array indexing? [duplicate]

This question already has an answer here: How does the logical `and` operator work with integers in Python? [duplicate] 2 answers Python's Logical Operator AND 6 answers I found one code that used A[i][j] += min(A[i - 1][j and j - 1:j + 2]) I tried similar implementation as shown below which gave...
Karan Shah
1

votes
2

answer
455

views

automatically appends string in strcat function

I am having a problem with strcat() function. Please explain me how that function works. char a[] = 'AT'; char x[] = 'KA'; char y = 'X'; sen(a); s = strcat(a, '+CMGF='); sen(s); s = strcat(s, '\r\n'); sen(s); s = strcat(s, &y); sen(s); getch(); return 0; S is a glopal character pointer & sen() is a...
Karan Shah
2

votes
0

answer
86

views

Google Home dialogue flow agent authentication error

Error:- Buckets: Exception in thread 'main' java.lang.NoSuchMethodError: com.google.api.services.storage.Storage$Buckets$List.setUserProject(Ljava/lang/String;)Lcom/google/api/services/storage/Storage$Buckets$List; at com.google.cloud.storage.spi.v1.HttpStorageRpc.list(HttpStorageRpc.java:311) at co...
karan shah
2

votes
5

answer
158

views

Not able to understand if in #define

Can anyone help me to understand the meaning of this line? I know it's kind of macro structure, but what does , suggest in the code?? #define ReturnErr(fCall) if (iErr = (fCall), (iErr != NO_ERRORS)) {return iErr;}
Karan Shah
3

votes
1

answer
1.2k

views

Multiple Clock Assertion in Systemverilog

Here is the Design Code : module mul_clock (input clkA, clkB, in, output out); bit temp; reg x[2:0]; always @ (posedge clkA) temp @(posedge clkB) (out == x[2] ^ x[1], x[1] = x[0]) |=> @(posedge clkB) (out == x[2] ^ x[1], x[2] = x[1]); endproperty Note : With always block and a single clock asserti...
Karan Shah