Questions tagged [rtl]

1

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1

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775

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Proper way to reset a SC_THREAD in SystemC from another process

If I have two threads in SystemC, A and B (both SC_THREAD), and I want thread A to stop executing (be reset) if a variable or event in B gets asserted, what is the proper way to accomplish this. Here is a more illustrative example: // Thread A: Data transfer SC_THREAD(rx_tx_transfer); dont_initializ...
evilpascal
1

votes
1

answer
94

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Non blocking Statements execution in verilog

I am new to verilog, can anyone please explain me how does these statements execute. [email protected](posedge clock) begin A
Naveen Kumar
1

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1

answer
157

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Power operator in Chisel

I am trying to find an equivalent of Verilog power operator ** in Chisel. I went through Chisel Cheat sheet and tutorial but I did not find what I was looking for. After going through designs written in Chisel, I found that log2xx functions are popular choice while the power operator is never used....
maskarih
1

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2

answer
1k

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How to resolve “Register/latch pins with no clock driven by root clock pin” error in Vivado?

As a learning exercise I am doing some HDMI experiments on an FPGA using VHDL. When coming to implement it in Vivado (2017.1) I am encountering the following warning in the timing report: There are 11 register/latch pins with no clock driven by root clock pin: Hsync_i_reg/Q (HIGH) I have opened the...
epsilonjon
1

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4

answer
258

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Looking for HTML to PDF package in RTL for LARAVEL

I've been searching and experimenting with packages, and I can't find a Laravel package for converting and downloading PDF (based on a HTML view), that works for RTL. Does anyone have any experience with a working package for Laravel 5?
user1037607
1

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1

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59

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How to remove unwanted output in VERILOG?

I am working on very large module in which this multiplier and adder module is a small part but it will help me to express my question here. RTL code: module mul_and_add #(parameter BITS = 32, parameter SHIFT = 15 ) ( clk, i_multiplicand, i_multiplier, i_adder, o_result ); input clk; input signed [...
Shaown
1

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2

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616

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Inactivity Kill-switch for SystemVerilog Testbench Simulation (VCS)

Hi and thanks for seeing this. I was pondering over the idea of an inactivity killswitch for SystemVerilog simulation. Is there a way in which a prolonged (programmable) duration of inactivity when running 'simv' can trigger an internal event to call '$finish' ? Or is it possible using the VCS comm...
boffin
1

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1

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2.2k

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Defining parameters from command line in (system)verilog simulation

I have a module ''constrained'' with several delays as parameters. I want to simulate all the possible configuration of the delays in the module. As I have a lot of configuration to test, I do not want to instantiate all the configuration possible in the same testbench. The idea I had was to launch...
Krouitch
1

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0

answer
26

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iOS side-loaded expo app horizontally flipped

I'm using expo in my react native project. Everything is fine when loaded to either Android or iOS emulators. However when I side-load it to my actual iOS phone device, everything is flipped. The header hamburger menu goes to the right even though the drawer still animated from the left. Text excl...
1

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1

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83

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Clock Conversion for RTL Verilog (FPGA) Synthesizable Code

Converting 12 MHz system clock signal on FPGA to 1 MHz Signal output at a 50% duty cycle. I understand that I need to divide by 2 @ 50/50 duty cycle to get 6 MHz, and then divide by 2 again to get to 3 MHz, and then divide by 3 to get to 1 MHz. Is this the correct method? Also, how would I implement...
tnet
1

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2

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25

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rtl-sdr crashes with “Bus error” when running rtl_tcp or rtl_test

I have an SDR dongle connected on a Raspberry Pi 3 running Kali Linux Arm64. The SDR itself is this particular model Trouble is, whenever I connect to the rtl_tcp server remotely, it exits: rtl_tcp -a 192.168.200.132 Found 1 device(s): 0: Realtek, RTL2838UHIDIR, SN: 00000001 Using device 0: Generic...
Upvote Me
18

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1

answer
1.9k

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Strange behaviour of TParallel.For default ThreadPool

I am trying out the Parallel Programming features of Delphi XE7 Update 1. I created a simple TParallel.For loop that basically does some bogus operations to pass the time. I launched the program on a 36 vCPU at an AWS instance (c4.8xlarge) to try to see what the gain of Parallel Programming could be...
Pep
15

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5

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16.4k

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Arabic language with Sublime Text editor

I have a problem with sublime text editor that RTL languages are not supported! I try this plug in Bidirectional text support with windows os I have copied all files from the zip Sublime-Text-2-BIDI-master into the ST3 folder and changed the font type and size... then I copied over the unicodedata....
Dania Delbani
3

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1

answer
179

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Using berkeley hardfloat

I am using Chisel3 in my project. I tried to import hard float library as folow: import chisel3._ import hardfloat._ but unfortunately, I am getting: [warn] :::::::::::::::::::::::::::::::::::::::::::::: [warn] :: UNRESOLVED DEPENDENCIES :: [warn] :::::::::::::::::::::::::::::::...
maskarih
9

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1

answer
1.4k

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How to handle mixed RTL & LTR languages in notifications?

Background Android 4.3 has added a lot of support for RTL (Right-To-Left) languages, such as Hebrew and Arabic. The problem Even though there is 'textDirection', 'layoutDirection' and 'gravity', I can't find the equivalents for the notification builder, not even in the compatibility library. This me...
android developer
2

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1

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1.5k

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Verilog apply force to module output without changing internal state

In my testbench, I want to simulate a system condition by forcing a certain module's output in the RTL: force DUT.driving_module.xx = 0; But when doing this with the force command, the wire that drives the output inside the module is also forced, which leads to other parts of the system being also a...
chinocolerico
2

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1

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73

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Query for VHDL synthesis for IC Design (Not FPGA), specifically in case of variable assignment

If for a given process, I declare a variable (let's say a 1 bit variable, variable temp : std_logic;) then can I assign a value to the variable if a given condition returns true, i.e. if (xyz=1) then --Assuming that this condition returns TRUE temp:= '1'; ?? Will this logic be synthesizable for ASI...
Gaurav Singh
1

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2

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826

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IC design/verification with Python [closed]

I see a lot of jobs in this field asking for Perl and Python scripting experience. Very little C programming if any. Where HDL is the main focus (verilog,, VHDL) along with digital system design knowledge. Is Python generally used in these job roles as an industry standard or as an 'unofficial st...
cc6g11
3

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2

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19.9k

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display vs strobe vs monitor in verilog? [closed]

What is the difference between display vs strobe vs monitor in verilog?
blitz
2

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2

answer
750

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D-flip flop with 2 reset: synthesis error

I'm doing a synthesis of a digital block and I need a D-Flip-Flop with 2 asynchronous resets. (The reason is that I will drive one reset with an available clock, and I will use the second one to reset all the registers of my digital block) I prepared the following code: module dff_2rst(q,qn,clk,d,...
clidre vandijk
3

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5

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755

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FPGA based RTL evaluation

Currently I am testing some RTL, I am using ncverilog, and it is very ... very slow. I have heard that, if we use some kind of FPGA boards, then things will be faster. Is it for real?
Alphaneo
1

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1

answer
609

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How to write a synthesizable RTL that can count rise and fall of a signal

I want to measure the number of rise transitions and fall transitions of a signal. I am using the signal as a clock and implemented 2 counters. One counter increments on every rising edge and another increments on every falling edge. I am adding the result of these 2 counters to get the final count...
Neela Lohith
2

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1

answer
3.2k

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VHDL: Assigning elements from a 2D array to 1D array

I have a 2D array of records which I have to select column by column for processing. I am marshaling the column records into a column array, something like this: col_array(0)
boffin
2

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3

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1.1k

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Issue with SystemVerilog for loop having non-blocking assignment?

As I was working on a SystemVerilog based FPGA design, I came across a situation where I had to compute the sum of an array of 4 elements on a clock edge. I was able to do that using a for loop with non blocking assign statements. The design synthesized successfully on Quartus 15.0 but when I tried...
electro_sm11
3

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1

answer
52

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passing arguments to verilator backend in chisel

i have wrote a simple PeekPokeTester testbench in chisel and it compiles and run successfully using verilator backend. but now i want to pass some flags to verilator backend. in driver options there is a '--more-vcs-flags' option but there is not a similar thing for verilator. is there any way to ch...
Amin Habibi
2

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2

answer
4.4k

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Override size of a parameter that is an array of a struct in systemverilog

i have a module parameter that is an array of a predefined struct. I set the default size of this array as 1 element. The idea is to override it with the appropriate size at the time of instantiation. The way i show below doesn't override the size. It only overides the first value. I can see w...
shparekh
2

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2

answer
1.9k

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Disable auto change layout direction while using android:supportsRTL=“true”

My application must support both RTL and LTR languages in the future but for now just RTLs. When I use android:supportsRTL='true' with android:layoutDirection='end' in each layout, NavigationView and Toolbar and everything else are fine. But the only problem is when user change system language to a...
Abolfazl
7

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1

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2.6k

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How can I use TTask.WaitForAny from the new threading library?

In an attempt to use the threading library in Delphi to calculate tasks in parallel and using TTask.WaitForAny() to get the first calculated result, an exception occationally stopped the execution. Call stack at the exception: First chance exception at $752D2F71. Exception class EMonitorLockExceptio...
Jimmy Dean
3

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5

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2.2k

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Why do we use Blocking statement in Combinatorial Circuits designed using Always Block in Verilog/Systemverilog ? Why not Nonblocking?

Everywhere it is mentioned this as a guideline, but after lot of thought i want to know what harm will it cause if we use Nonblocking statement inside Always Block for Combinatorial also. I won't be mixing the two together. But what i feel is when we use Nonblocking for Combinatorial statements in A...
Edwin Joseph
2

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1

answer
179

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Can I create a new Jfrog Artifactory package type plugin?

I want to store RTL modules (Mostly VHDL files - .vhd) in Artifactory, and be able to trace the dependencies of those packages with Xray and the other Jfrog services. I already have a pretty clean 'package' format, I just want to have Artifactory parse my meta-data files on upload that are part of t...
Jedidiah Bartlett
4

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1

answer
1.4k

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Parameterized Bit-fields in verilog

Is it possible to parameterize a bit-field in verilog? Essentially I want to use a parameter or alternative to define a bit-range. The only way I can think of doing this is with a `define as shown below but it seems like there should be a better way. `define BITFIELD_SELECT 31:28 foo = bar[BITFIELD_...
funkyeah
6

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3

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5.6k

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Program to create a Verilog block diagram

I want to create a program to parse Verilog and display a block diagram. Can someone help me regarding what algorithms I need to look into? I found a good Verilog parser, but now I need to find the relation between each block and place them accordingly. It does not have to be extensively optimized....
user591124
1

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2

answer
1.8k

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How to pass parameters to a verilog module when performing synthesis?

I have a parameterized verilog module with a bitwidth that is variable depending on the value given in `define WIDTH. However, I would like to be able to somehow change the value of WIDTH by passing in a parameter during synthesis using design compiler. I was wondering if there is a way to do this?...
Veridian
3

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1

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895

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Passing a module name as parameter

I want to create this generic wrapper for a bunch of modules I am writing. The wrapper should provide the ability to connect these modules to different type of NoCs without having to change the behavior of the inner modules. I thought that one way to do this would be the following. Considering a ver...
igon
3

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3

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519

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Is it necessary to seperate combinational logic from sequential logic while coding in VHDL, while aiming for synthesis?

I am working on projects which requires synthesis of my RTL codes specifically for ASIC development. Given the case, how much important is it, to separate sequential logic from differential logic while designing my RTLs ? And if it is important, then what should be my approach while designing, as if...
Gaurav Singh
1

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4

answer
1.9k

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verilog or systemc for testbench

I am assigned with the task of verifying some verilog based RTL code. Now, coding the RTL testbench using verilog seems to be very difficult (for me). So I would like to try one of the following. - Try providing a PLI interface to the RTL and thereby invoke 'C functions for testing - Using system 'C...
Alphaneo
2

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0

answer
180

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Synthesizing SystemC with Vivado doesn't give desired VHDL signals

I am writing a project is systemC and i have a couple of sc_in and sc_out to communicate between my modules. When I synthesize the project, in the vhdl code produced each sc_in and sc_out creates a block of signals like this: valid_in_address0 : OUT STD_LOGIC_VECTOR (2 downto 0); valid_in_ce0 : OUT...
PetrosM
3

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1

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985

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Present State of Random Number Generator in System Verilog

How we can get the present state or present seed of Random number generator in system verilog??
user1511590
2

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1

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503

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Force VHDL to use generic over constant

I have some VHDL where a generic is the same name as a constant in an imported package. NCSIM seems to use the value of the constant from the package over the generic. Rather than rename the generic is there a way I can force the scope to pick up the generic.
user1223028
8

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2

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10.8k

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How to define and initialize a vector containing only ones in Verilog?

If I want to declare a 128 bit vector of all ones, which one of these methods is always correct? wire [127:0] mywire; assign mywire = 128'b1; assign mywire = {128{1'b1}}; assign mywire = 128'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;
Veridian

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