Questions tagged [instruction-set]

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BGE Instruction ARM

This test asks to branch under the condition 'BGE' branch to a label. The values stored in my registers being compared are: LDR r0,=0X3 LDR r1,=0X8F CMP r0,r1 BGE a_label SUBS r1,r1, #0XC9 I expected it to branch but somehow 0X8F isn't greater than 0X3. Emulating my code on Keil proves this. Im wond...
MangoKitty
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Pushing imm32 ends up in pushing imm64? [duplicate]

This question already has an answer here: How many bytes does the push instruction push onto the stack when I don't specify the operand size? 2 answers push on 64bit intel osx 4 answers From the intel instruction reference: 68 id PUSH imm32 It means pushing dword-sized immediates is valid in 64-bi...
St.Antario
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Calculating an instruction size manually

I am trying to learn how to convert a single assembly instruction to OP code manually. I'm looking at PowerPC instruction set which has a fixed 4 byte instruction length as an example. The folloing example is written in my reference: One effect of fixed-size instructions is you can't load a 32-bit c...
John
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How to convert Stack based instructions to Register based

This is what I have tested with the dis module in python - >>> def f(): ... a = 1 ... b = 2 ... c = 3 ... a = b + c * a ... return a + c ... >>> dis.dis(f) 2 0 LOAD_CONST 1 (1) 2 STORE_FAST 0 (a) 3 4 LOAD_CONST 2 (2) 6 STORE_FAS...
Dean
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AMD Open64: Optimized math functions

Does Open64 has something equivalent to Intel Short Vector Math Library Operations. Thank you.
pic11
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Software Stack for a Particular computer

I am working on a project and my team is responsible for the software stack of the particular hardware. I only have the instruction set of the processor in my hand and I need to develop the complete software stack with it. Do I require anything else other than the instruction set for the assembler?...
anichhangani
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Difference between “load word” and “load linked word” in MIPS

I am wondering if somebody could explain to me the difference between the LW (load word) and the LL (load linked word) instructions are in MIPS? I cannot seem to find any online sources that distinguish the two from each other and my book does not seem to distinguish them form each other either at t...
audiFanatic
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_mm256_xor_si256 for xoring two regions meets a core dump error

For fast XORing two regions of memory, I wrote a function(region_xor_avx()) with AVX instructions optimized. However, the program met a core dump error at _mm256_xor_si256(). Here is a short self-contained example: #include #include #include int region_xor_avx(void *dst, void *src, int len){ int...
foool
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Defining and Using Global Variable in PowerPC Assembly file

I want to save the contents of a SPR ( Special Purpose Register ) to a global variable. I don't have much experience in Assembly, but i tried to do it as follows : .global __The_Global_Variable mfspr r16, 695 #695 is the number of the SPR Register stw r16, __The_Global_Variable #I get Syn...
Maged Rawash
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How instruction set randomization works, roughly

I read about instruction set randomization in modern processors where a processor randomizes the instruction sets to avoid code injection attacks. Actually, Wikipedia explanation is not clear to me. Kindly, can someone explain the process of it in a clear way? Is there a key involved?
Kristofer
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How to use the enhanced multiplier instructions of ARMv5TE instruction set

I'm using an ARM966E-S RISC-CPU and was wondering how to use the apparently available instruction set extensions for better DSP performance, e. g. an enhanced multiplier instruction. I've read in the technical reference manual that these instruction set extensions are available but I don't know how...
Iniesta8
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32-bit fixed instruction length in 64-bit memory space

I am currently reading up on the AArch64 architecture by ARM. They are using a RISC-like instruction set with a fixed instruction length of 32-bit while operating on 64-bit addresses. I am still new to the topic of ISA so my question is: how can you operate with 64-bit long addresses when you only h...
SuperTasche
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Direct Arithmetic Operations on Small-sized Numbers in RISC Architectures

Are there any RISC architectures which allow arithmetic operations to be applied individually to bytes, half-words and other data cells, whose size is less than the size of the CPU general purpose registers? In Intel x86 (IA-32) and x86-64 (known as EM64T or AMD64) processors not only the whole regi...
Victor
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Risc-v instruction that i dont understand

I have this risc v code : lui S0, 0x1234 ori S1, S0, 0x5678 add S2, S1, S1 and the question asks me, 'What does the register S2 hold?' The question explains that lui and I quote: 'Load the lower half word of the immediate imm into the upper halfword of register rt. The lower bits of the register...
Razi Awad
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Left Shift Logical by sum of two numbers/registers?

Is there a way to perform a left shift logical by a sum of two numbers/registers? I am thinking of something that looks like this, but actually works: mov r4, r1, lsl add, r7, #1
brunshte
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What is the AMD ryzen 7 2700 instruction set (for creating an assambler)

I want to create my first assembler so I can program my own program languages, my own OS and so on. There's just one problem: I can't find an instruction set for the ryzen 7 2700. I already found out that it uses the zen+ architecture but I couldn't find something for this either. Does anyone know w...
Dzenan
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Is my understanding of lw instruction in MIPS correct?

I am just starting to understand MIPS, and the particular instruction 'lw' confuses me. From the thread, Understanding how `lw` and `sw` actually work in a MIPS program, this is what I have gathered: If, say, we have: lw a, 4(b) // a and b are registers Then, it just means that we will get the data...
Tina
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How to find the time value of operation to optimize new algorithm design?

My question is specific to iPhone, iPod, and iPad, since I am assuming that the architecture makes a big difference. I'm hoping there is either a specification somewhere (for the various chips perhaps), or a reliable way to measure T for each specific instruction. I know I can use any number of tool...
Rab
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Instruction set simulator(SystemC) for MIPS architecture

Does anybody know if there is a open source MIPS instruction set simulator (in C++ or SystemC preferably)? I googled dozens of links and there is just no open ISS of MIPS cpu. Then only ones I know for now is Plasma CPU, which implements only a limited number of mips instructions, thus some applica...
lukmac
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Computer architecture homework - instruction operands

A digital computer has a memory unit with 32 bits per word. The instruction set consists of 150 different operations. All instructions have an operation code part (opcode), a register operand part (specifying one of 10 different registers) and a memory operand address part. Each instruction is...
mavix
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Which are the different variable cycle ARM instructions?

I was reading this book 'ARM System Developers Guide' by Elsevier and I came across this: The ARM instruction set differs from the pure RISC definition in several ways that make the ARM instruction set suitable for embedded applications: Variable cycle execution for certain instructions — Not ev...
HaggarTheHorrible
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Confused about the binary code for the MVI instruction in the 8085 instruction code. Please see

Consider the instruction MVI A,32H to load 32H in the register A (Intel 8085 Microprocessor). My book says that it is a two byte instruction where the first byte is the opcode and the second is the operand. The first byte being 0011 1110 (3E in hexadecimal) and the second byte being 0011 0010 (32 in...
finitenessofinfinity
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Complex Instructions and Pipelining

I am reading Computer Organization and Design by P&H and came across the following line: 'in an instruction set like the x86 where instructions vary from 1 byte to 17 bytes, pipelining is considerably more challenging', where the comparison being made is between x86 and MIPS. Does a longer instruc...
vrume21
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Byte Manipulation for MIPS instruction set

I would like to do some byte manipulation using MIPS instruction set. I have register $S0 which has 0x8C2E5F1E and register $S1 which has 0x10AC32BB. I would like to store the second byte of $S0, 5F, into the third byte of $S1, AC. My logic would be to store the byte of register $S0 into another re...
Salchem
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List of Instruction Sets for Android

In an app I am developing, I need to use a C library. This means I'm going to have to deal with all the different instruction sets of all the different Android devices, right? Is there any list available (or maybe somebody can just tell me?) of all these instruction sets? I know that all Android de...
Zero
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Why does the 80x87 instruction set use a “stack-based” design?

Back when Intel first designed the 8087, why did they choose to organize the floating-point registers as a stack? What possible advantage could be gained from such a design? It seems much less flexible and harder to work with than allowing arbitrary registers to be used as source and destination ope...
Alex D
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Opcode and funct code in MIPs Assembly

My professor takes forever to answer emails, reasonably so since its Saturday, so I just wanted to ask here instead. I read here that the funct code defines what the function being used is (add, sub, etc) and the opcode defines the format (R,I,J)...but then how does the I format know what funct to...
user2052752
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What address I could access with LDR instruction of ARM

I'm totally new for ARM assembly code. I just checked the instruction set and found there is an instruction LDR which could be used as 'LDR{}{} Rd, '. I have two questions about this instruction: 1) Is the address here physical address or virtual address? 2) How could I know which address is 'legal'...
S.Wan
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Differentiate data from instructions in ARM

In (32-bit) ARM Linux kernels, how to differentiate data embedded in the code section, from instructions? It is better to have a light-weight approach, like bit masks, which can be easily implemented. It is not wise to embed a dissembler into the kernel.
WindChaser
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MSP430 SWAP bytes explanation assembly

When we have a code like this : main: MOV #SFE(CSTACK), SP ; set up stack ;;; some instructions ....... ; load the starting address of the array1 into the register R4 MOV.W #arr1, R4 ; load the starting address of the array1 into the register R5 MOV.W #arr2, R5 ;...
user629034
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What control lines are asserted/set to 1 when a load double word instruction is called?

Using this diagram, I am looking at this instruction to determine what control lines are necessary. ld x5, 40(x9) x5 = 0x000000ff x9 = 0x00000fff I am curious what control lines (RegWrite, MemRead, MemWrite, MemtoReg, Branch, Zero, ALUSrc) are asserted or set to 1 in order for this instruction to...
Megan Byers
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Does a memory barrier acts both as a marker and as an instruction?

I have read different things about how a memory barrier works. For example, the user Johan's answer in this question says that a memory barrier is an instruction that the CPU executes. While the user Peter Cordes's comment in this question says the following about how the CPU reorders instructions:...
Steve
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How to run Windows from an emulator on a non x86 host machine?

Windows runs on x86 based CPUs only. Is it possible to make Windows run on non-x86 architecture CPUs like POWER, SPARC, ARM, etc.... I know that there is a program viz., Virtual PC 7 for Mac that allows Windows to be run on PowerPC inside MAC OS but not much detail available.... I'm talking about vi...
user243093
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solving an assembly with instruction sets (Fibonacci) *urgent help*

The function F is defined as F(1) = F(2) = F(3) = 1 and for n ≥ 3, F(n + 1) = F(n) · (F(n − 1) + F(n − 2)) i.e., the (n + 1)th value is given by the product of the nth value and the sum of the (n − 1)th and (n − 2)th values. (a) Write an assembly program for computing the kth value F(k),...
dabbing king
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How do register numbers affect number of loads and stores in ISA?

I am trying to solve a question about register numbers in instruction set architecture. The question is; Suppose that the code sequence is to compute A=B+C, B=A+C, and D=A-B. Assume that all of A, B, C, and D are initially in memory. List the sequence of instructions for Register (load-store) ISA, a...
mancini13
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Why does the 6502 microcontroller not have a arithmetic right shift?

I'm trying to understand the instruction sets of old microcontrollers, especially the 6502. The documentation of the instruction set that can be found here lists two shift instructions (beside the rotate instructions): ASL - arithmetic shift left LSR - logical shift right Why are there no arithmetic...
uzumaki
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In buildroot, how to enable deprecated features?

I have to compile C for mips that uses MIPS1 instruction set, but Buildroot no longer supports MIPS1 instruction set (See the bottom of this page: http://buildroot.org/downloads/manual/manual.html). Could you please let me know how to enable the deprecated feature (i.e., MIPS1 instruction set) in Bu...
freddy
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g++ dumped assembly output doesn't work

I have following C++ code in main.cpp file. int add(int a,int b) { int c = a + b; return c; } int main() { int a = 2; int b = 4; int d = add(2,4); } when I ran g++ -S main.cpp I got the following assembly code.(after removing all the debug symbols). Also I have changed the code to print the sum of t...
sampath
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About arm pc value in thumb 16/32bits mixed instructions stream

I read a couple of articles including question here in SO Why does the ARM PC register point to the instruction after the next one to be executed?, that pc register value is actually current executing instruction address plus 2 instructions ahead, so in ARM state it's +8 byte (2*32bits). My question...
Bill Randerson
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aesimc instruction gives incorrect result

I'm trying to implement AES cryptography using the AES machine instructions (basing it on Intel's white paper) available on my Sandy Bridge. Unfortunately, I've come to a halt in the phase of generating the round keys for decryption. Specifically, the instruction aesimc (applying the Inverse Mix Col...
Morten Kristensen

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