Questions tagged [cpu]

1

votes
3

answer
507

Views

Do modern CPU's have compression instructions

I have been curious about this for awhile since compression is used in about everything. Are there any basic compression support instructions in the silicon on a typical modern CPU chip? If not, why are they not included? Why is this different from encryption, where some CPUs have hardware support...
Trevin Corkery
1

votes
2

answer
156

Views

Insufficient cpu in Kubernetes multi node cluster

I am trying to deploy an application into my Kubernetes cluster. It is a multi node cluster. There are 3 m4.2xlrge aws instances. m4.2xlarge vCPU :- 8 Memory :- 32 Now, in my deployment.yaml file for that service, I have mentioned limit: cpu: 11 request: cpu: 11 It is giving error, insufficient cpu...
Dinesh Ahuja
1

votes
2

answer
36

Views

Calculating which compiler is faster in terms of cycling

I just have a simple question, a bit silly, but I just need some clarification for an upcoming exam so I don't make a stupid mistake. I am currently taking a class in computer organization and design and am learning about execution time, CPI, clock cycles, etc. For a problem, I have to calculate th...
Janeson00
1

votes
1

answer
24

Views

What is non-idempotent memory-mapped I/O meaning?

In RISCV privileged spec page 75 mention a term 'non-idempotent memory-mapped I/O'. What is non-idempotent memory-mapped I/O? Is it about non side effect?What is design concern about non-idempotent memory-mapped I/O?
tommycc
1

votes
1

answer
34

Views

Program suddenly has a spike in cpu usage and looks like it is paused

I have added 2 functions: int aiCheckScore(char arr[7][7], int inp, int height, Player player) int aiFindMostRelevant(char arr[7][7], Player player) The first makes a score for a given position in a 2D array. The score is equal to how many of the same kind elements we would have in a row (verticall...
alex999ar
4

votes
3

answer
113

Views

How can I get the CPU usage of a process with “tasklist” in Windows

I am writing a program in Java to periodically display the CPU and memory usage of a given process ID. My implementation invokes tasklist. It is pretty straightforward to get the memory usage by the following command: tasklist /fi 'memusage ge 0' /fi 'pid eq 2076' /v This will return the memory usag...
JakeSmitch
1

votes
1

answer
2.9k

Views

Get Thread Cpu Usage

I have a set of cpu consuming executions that each run in thread with low priority. These threads will be run in a Process (Like IIS) that have many other threads that I don't want to slow them. I want to calculate the cpu usage of all other threads and if its greater than 50% then i pause one of my...
mrd abd
1

votes
4

answer
743

Views

Preventing or blocking cpu data cache loading

I'm tasked with evaluating various flavors of ARM processors (benchmarking), specifically System On a Chip (SOC). Some SOC's have a lot of data cache, others have little. Because of this, I'd like my program to block the data cache. I have written a Walking 1 test which accesses memory outside t...
Thomas Matthews
1

votes
2

answer
234

Views

What is meant by memory-mapped video?

What does memory-mapped video means? For example, on a x8086 Intel CPU, it has a 20 bit address line. Does this memory-mapped means some of the x8086 address lines are hardwired to the video adapter card?
thirstForKnowledge
1

votes
1

answer
102

Views

About data hazard and forwarding with beq in MIPS?

Why the first add needs forwarding? # stage: add $1, $2, $3 # WB add $4, $5, $6 # MEM nop # EX beq $1, $4, target # ID Since beq needs the $1, if the first add is about to execute WB-stage, isn't that no forwarding needed since beq at ID-stage, which is about to read the r...
BinaryTreeee
1

votes
2

answer
29

Views

What are the pros n cons of Multicore Processors and Multithreaded Processors (SMT) [closed]

With SMT parts of the one processor are shared between threads, while other parts are duplicated between them On the other hand, multi-core processors embed two or more independent execution cores into a single processor package. My question: What are the Pros n Cons of each architecture's in differ...
Zinedin Zidane
1

votes
3

answer
1.1k

Views

Do programmable Ethernet devices (think onboard CPU) really exist?

I've heard from various people that programmable Ethernet cards exist and are easily available. However I have yet to be able to track down one of these mythical devices so I'm wondering if they're just that - a myth. Such a programmable card has a gigabit Ethernet interface, has a programmable CPU...
PeterM
1

votes
0

answer
105

Views

Unpredictable results in calculations under Cortex-A53

The Java code below returns unpredictable results when ran on a Cortex-A53 and specifically on Xperia XA devices. The first iterations print the correct values: [24, 42, 61, 45, 29, 46, 35, 36, 48, 47, 20, 64, 45, 15, 37, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70] and after some...
Petrakeas
1

votes
0

answer
62

Views

Process Cpu time increases gradually

In our linux systems we observe that cpu load, heap usage of a java server is normal but OperatingSystem.ProcessCpuTime is gradually increasing, drops to minimum value and increased again. We have 2 cores in linux system. could you clarify me on these below: 1) as example in above picture, what is...
santosh.a
1

votes
0

answer
65

Views

MIPS memory model: Compiling software to run in KSEG0 or KSEG1

In the MIPS memory model both KSEG0 and KSEG1 map to the same physical addresses but KSEG1 is uncached while KSEG0 is cached. The argument for this is that you can dynamically decide to run code either Cached or Uncached. My question is: how do you actually compile code which runs in either virtual...
FourierFlux
1

votes
0

answer
327

Views

How does the CPU knows which interrupt service routine to run against a hardware interrupt?

For example, a key on a keyboard is press causing a hardware interrupt to be generated to the CPU, the CPU sends an acknowledgement to the interrupt controller. At the stage of the interrupt process, how does the CPU knows which interrupt service routine to run based on a key press on the keyboard?
thirstForKnowledge
1

votes
0

answer
379

Views

function to perform swapping in an array

The basic flow of the program is as follows: 1. Print the original content of array. 2. Ask the user for two indices X and Y. 3. Swap the two elements if Array[X] > Array[Y]. 4. Print the modified array only if swapping occurs. .data array: .word 8, 2, 1, 6, 9, 7, 3, 5, 0, 4 newl: .ascii...
greenland
1

votes
1

answer
60

Views

How is Linux dealing with blocking I/O processes

I have a system that does a lot of blocking network calls. Based on that the CPU idle time is relatively high as well as the overall system load. When I add more CPUs to the system idle time remains the same but system load drops. Why is that happening? Is the following what is happening behind the...
mike
1

votes
1

answer
34

Views

Application process' speed [closed]

I am making a specific programm, and it is done in 99%. It computes very big amount of numbers, though, the program does it very slowly. My programm uses only 10% of CPU despite that fact that there is 60% of it free. How can I force it to 100% (power options set to 100% usage)? How can I force th...
Łukasz Szurek
1

votes
0

answer
245

Views

Java - Write Excel Using POI, CPU consuming

My program generate some Excel using apache POI. This part take up 50% of CPU for 1 excel.. If users generate at the same time multiple excel the server is out... How can i reduce it ? final Workbook workbook = new HSSFWorkbook(); initDataFormat(workbook); EnumMap sheetMap = sheetMap = BomXlsSheetEn...
Alexandre
1

votes
0

answer
17

Views

Address sections of a 32-bit registers

During a lecture about CPU registers. The lecturer told us about 32-bit registers and the sections of such a registers. He told us that there is no way to address the upper sections of a register. This made me wonder what he meant with the upper sections of a register. Does he mean the AH section o...
Toine-L
1

votes
0

answer
113

Views

Breakup of MEM_LOAD_UOPS_RETIRED.L3_MISS event in Intel Broadwell-EP

I am trying to compare the coherence and DRAM access cost for an application. For this, I am thinking of measuring L3_MISS (specifically MEM_LOAD_UOPS_RETIRED.L3_MISS) events and compare it to HITM events (specifically MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM and MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_...
YetAnotherPseudoName
1

votes
1

answer
113

Views

LLVM physical register mapping

I have some function in LLVM IR, which has some input arguments. However, I want to keep an argument passed in a register, and I want to compile it only for x86. For instance, I am writing a function containing adding instruction: %sum = add i64 %val1, %val2 and no matter which args are in the list,...
ultrablox
1

votes
0

answer
82

Views

MIPS assembly - subroutines and functions inquiry

I'm fairly new at this type of 'programming' so I've encountered some problems while creating a program. The program that I'm trying to create accepts two integers, n and r. If n is equal to r, OR r is equal to 0, the value of the output is 1. Otherwise, it will implement an f(n-1,r) + f(n-1,r-1) fu...
Kim Chaeyoung
1

votes
0

answer
85

Views

Finding CPU Platform Name and Family

I’ve been Googling all morning trying to find a way to use VB.Net code to find the platform and family of my CPU. For instance: Intel Xeon (Haswell) OR Intel Xeon (Sandy Bridge) I have a program I’ve been working on that has several different versions specifically optimized for certain CPU plat...
user854695
1

votes
0

answer
53

Views

Why does the AWS-EC2 CPU utilization drops gradually while the same python script is running?

I have a python script running on Amazon Web Server. Initially the CPU utilization is high, ~60%. However it gradually drops to between ~0-1% rate and ranges around there while the same script runs. Why does this happen? My python script is as follows: `import numpy as np pd.set_option('max_colwidth...
David Dawei
1

votes
1

answer
116

Views

Page table size, virtual memory size and physical memory size

The memory architecture of a machine has: +-----------------------+-------+ | Virtual address: | 48-bit| | Page size | 8 KB | | Page table entry size | 32 bit| +-----------------------+-------+ Let's pretend that 4 bits from page table entry are used by OS to determine the access r...
greenland
1

votes
1

answer
637

Views

GPU vs CPU end to end latency for dynamic image resizing

I have currently used OpenCV and ImageMagick for some throughput benchmarking and I am not finding working with GPU to be much faster than CPUs. Our usecase on site is to resize dynamically to the size requested from a master copy based on a service call and trying to evaluate if having GPU makes se...
gegupta
1

votes
0

answer
51

Views

Web Browser rendering

I am currently researching how the web browser works to render different frames and in-browser animations. Although there is a lot of information available on the Internet, none of the resources available seem to be suitable to answer my questions so any help would be greatly appreciated. These are...
Questionnaire
1

votes
1

answer
1.9k

Views

Optimize read from .gz file and cpu utilization python

Sample Input File: 83,REGISTER,0,10.166.224.34,1518814163,[sip:[email protected]],sip:[email protected],3727925550,0600,NULL,NULL 83,INVITE,0,10.166.224.34,1518814163,[sip:[email protected]],sip:[email protected]
van neilsen
1

votes
0

answer
282

Views

R studio one multi core CPU or dual single cores CPUS

So far I was using R on my home pc: i3 CPU, two cores, 4 threads. In order to run the code faster I was using the package 'DoSnow', utilizing 3 out of the 4 cores in order not to choke my system completely. However, now I got a server which has a two single core Xenons and I wonder: can I use the sa...
Mark2b
1

votes
0

answer
808

Views

Why does my Android device with ARMv8-based CPU cores (Exynos 7 Octa 7870) not support the arm64-v8a ABI or 64-bit instruction set?

I have an Android device (SAMSUNG Galaxy Tab Active2 SM-T397U) which has the Exynos 7870 SoC. The Exynos 7870 uses eight Cortex A-53 Cores that implement the Armv8-A architecture. However, it doesn't support the arm64-v8 ABI and it isn't clear which instruction set it supports. There are multiple An...
10seceonds
1

votes
2

answer
70

Views

Why does the output changes when i change the value of variables?

This is my code for FCFS CPU scheduling algorithm. When I replace j=1 then the output changes. #include #include #include main() { char pn[10][10],t[10]; int arr[10],bur[10],star[10],finish[10],tat[10],wt[10],i,j,n,temp; int totwt=0,tottat=0; //clrscr(); printf('Enter the number of processes:'); sca...
Rusher
1

votes
1

answer
215

Views

why op tf.tile() is always running on CPU even if I have set to run on GPU

this is the timeline from my training task, and it shows that op tf.tile() is running on cpu, and costs 1/3 of total time. I want to optimize it to accelerate the training speed. timeline from tracing log with tf.name_scope('key_masking'): key_masks = tf.sequence_mask(keys_length, tf.shape(keys)[1]...
Qinqin Tang
1

votes
0

answer
245

Views

Merge sort on simd register

Can anyone think of a way to perform merge sort on 8 elements of an simd register within 3 steps and 4 comparisons in each step? Thank you in advance!
siraxis
1

votes
0

answer
12

Views

Is there a way to determine how many CPU cycles my single-threaded program requires to execute?

I have a single-threaded, computationally intensive program and I would like to know if there is a way (such as a tool/profiler) that I can use to determine the number of CPU cycles my program requires to execute.
George
1

votes
0

answer
41

Views

Spring REST CPU usage limiting among endpoints

I have a Spring REST API. Let's say /students/122/gpa endpoint gives us GPA of the student with id=122 Let's assume that we are pre-calculating all GPA data and write into an HashMap. I don't want to query database for each request. The problem is: GPA calculation process (let's sat /calculate end...
Denny
1

votes
0

answer
86

Views

LRU Clock Replace Algorithm - What are reference bits initialized to?

Suppose I have a 2 entry TLB and am using LRU Clock replacement. Further suppose that I have a TLB miss and its a page fault, so I load in a page into memory and update TLB, now my TLB has 1 entry. Next, I have another TLB miss and its a page fault, so I load in a page into memory and update TLB now...
Harman Tatla
1

votes
0

answer
52

Views

downloading 32-bit vs 64-bit software

I have done a course that touches computer architecture a little bit, so I have a basic understanding of difference between 32 bit and 64 bit machine. What I don't understand is, why users sometimes are asked to download a correct version (32 bit or 64 bit) software? isn't that JVM (if the software...
amjad
1

votes
0

answer
37

Views

how does a modulus allow a negative number to be encoded

if x represents the value to be encoded and y is the number of decimal places to encode a decimal integer_to_big_endian(x * 10**y) % 2**64 how would the modulus ensure that negative numbers can also be encoded? Wouldn't a % of anything bigger than 2**64 give a remainder So I'm guessing if x * 10 **...
jim li

View additional questions