Questions tagged [cortex-m]

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Hardware timer triggered analog-digital conversion on ATSAM4S

I have a problem with a ATSAM4S ADC unit triggered by Timer 0 (channel 1). It seems that the ADC is triggered as fast as possible and blocks my whole application (OS is no longer operational due to this). I want an AD conversion with 1 Hz. This is my code: sysclk_enable_peripheral_clock(ID_TC1); uin...
user1995621
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.size in STM32f091XX startup file

I was going through a startup file of ARM cortex M0 STM32f091 controller.And i came across this:- .size __HeapBase, . - __HeapBase What does .size used for? What does the syntax given above perform?
Gaurav Sharma
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1

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Can DMB instructions be safely omitted in ARM Cortex M4

I am going through the assembly generated by GCC for an ARM Cortex M4, and noticed that atomic_compare_exchange_weak gets two DMB instructions inserted around the condition (compiled with GCC 4.9 using -std=gnu11 -O2): // if (atomic_compare_exchange_weak(&address, &x, y)) dmb sy ldrex r0, [r...
Groo
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1

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99

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Undefined reference to main when using Real-Time For the Masses

I'm trying to write a multi-threaded bare-metal application for the STM32F4Discovery using the Real-Time For the Masses (RTFM) crate. I've frankensteined together a minimal application from an example for the STM32F3Discovery board and this example: #![deny(unsafe_code)] #![no_main] #![no_std] exter...
arkap
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1

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Lua Crash When Creating a New State

I'm working on an embedded system with a Cortex-M4F with 256 kB of RAM and 1 MB of flash. My application is written in C++ but I built and integrated Lua as C library using GCC. I only had to define l_signalT as an unsigned 32-bit integer. My test code is the following: #include 'lua.hpp' int main(v...
Kenny
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2

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How to cross compile GSL library for arm-none-eabi-gcc?

I need to use the GSL library in my program on LPCXpresso 4367(ARM CORTEX M4). I tried to follow the library linking procedure for LPC xpresso but the MCU linker is giving me these errors: MCUXpressoIDE_10.3.0_2200\workspace\test1\Debug/../src/test1.c:53: undefined reference to 'gsl_linalg_LU_decomp...
Shreyas
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Configuring Memory Protection Unit on Atmel SAMD51

I am trying to configure the MPU of SAMD51 (Cortex-M4) to protect one 1k of FLASH from any access, and 1k of SRAM from write access that would contains sensitive information that should never be access or corrupted (from a SW bug or any other way). I wish to protect those sections, even in privilege...
pahpaul
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GCC some data outside sections

This is my linker file memory definition (Cortex M4 MCU with flash memory starting at 0x0 address): MEMORY { m_interrupts (RX) : ORIGIN = 0x0000A000, LENGTH = 0x00000410 m_text (RX) : ORIGIN = 0x0000A410, LENGTH = 0x00050BF0 m_data (RW) : ORIGIN = 0x1FFF0000...
Martin Dusek
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How to get a hard fault exception with a simple or instruction on arm

Currently we are hunting a phantom, which is in the form that when we compile in some code (without calling it) one specific call to memset generates an hard fault exception. The address and length given to memset are valid. Stepping through it in single instruction mode showed that it always fails...
Rudi
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34

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Cppcheck is returning different results on each scan

I'm trying to check embedded C code using Cppcheck (running on Windows 7, using GUI) but every time I click on 'Reanalyze all files' I get different results. The code is meaned to get build using GCC and running on a cortex M4 controller (STM32F4) I set the Paths and include paths (here only the roo...
viper1209
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sqrt function on stm32 arm doesn't work

I'm using an stm32f4 chip (cortex-m4) with an FPU and sqrt( 9.7 * 9.7 ) returns 94.17.. i am using the arm-none-eabi-gcc compiler and don't get any errors on compile. my makefile is really long because the same file is used for stm32f4 and sam4 chips. I don't even know the relevant parts to post....
swinman
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arm cortex-m least stack address and SRAM address relationship

I just read a guide of cortex M3 and M4. The memory map is a little confuse to me. The stack address sounds like start from 0x20007C00. and SRAM start from 0x20000000 to 0x20007C00? But how come microncontroller like STM32F407VGT6 has 192+4KB SRAM?
bli
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239

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Increment count for int8_t

I am working on cortex m0. I want to increment the count of a variable thats declared as int8_t but on displaying the output its pretty erratic. Code: // // Smpl_7seg_keypad // // Input: 3x3 keypad (input = 1~9 when key is pressed, =0 when key is not pressed // Output: 7-segment LEDs // #include...
Bluesir9
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1

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356

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LPC1114 bootloader-polling and user app-interrupts

Keil UV4 Dev System, LPC1114 Running bootloader: 0x0000.0000-0x0000.2000, user app: 0x0000.2000-0x0000.6000 Question - How to configure for Bootloader using polling and User App using interrupts I have been referring to NXP appnote 10995, and re-direction of interrupts, however- in this situation th...
whitedog
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2

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STM32F4 interrupt handler for capture its not called

The code below uses the capture compare feature of TIM1 channel 3 to capture rising edge on PE10, but its not working, the interrupt handler its not called. I am not that good at this embedded stuff, so can somebody tell me if I am settings this correctly ? #include 'STM32/stm32f4xx_tim.h' void TIM1...
Adrian
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1

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750

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gdb ARM Cortex-M exception Unwinding

I have been working with some Cortex-M4 (Freescale K60) devices with a compiled by me GCC (v4.7.2), BinUtils (v2.22), Newlib (v1.20) and GDB (v7.5). I have always been annoyed by GDB's inability to unwind from hard exceptions. recently I had an opportunity to use FreeScale's CodeWarrior, where I loa...
norton256
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ARM Cortex-M heap alignment

After being bitten by stack alignment problems I started wondering whether the heap should be aligned to 8-octet boundaries, as well. The ARM Cortex EABI states that for all calls to external functions the stack has to be 8-aligned. I could not find any information on whether there are any restricti...
DrV
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msp432 - Can code written for the TI MSP432 ARM Cortex M4 be ported automatically to other Cortex M4 microcontrollers?

I will preface by saying that I am fairly new to programming at the hardware level and that I'm interested in building apps based on the MSP432 microcontroller by Texas Instruments. I understand that to program this controller, one writes C code, links to the MSPWare library/drivers, and compiles...
Dan Kowalczyk
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1

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800

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va_arg on ARM Cortex-M4, uint64_t and GCC 4.9

I have the following piece of code: __attribute__((aligned(0x1000))) static void doVariadic(const uint32_t fmt, ...); __attribute__((aligned(0x1000))) va_list ap; __attribute__((aligned(0x1000))) uint32_t value1 = 0xABABABAB; __attribute__((aligned(0x1000))) uint64_t value2 = 0xF0F0F0F0E1E1E1E1LLU;...
jeremfg
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2

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745

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Can a SysTick exception in Cortex-M4 preempt itself?

I have a handler for SysTick exception which counts ticks and calls other functions (f1, f2, f3) whose execution time can be longer than SysTick period. These functions set and clear their active status (global variables) so if a SysTick exception occurs it can detect an overload and return to inter...
Zvonimir Mandic
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710

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How to access r11 register of ARM Cortex M3 with inline assembler of C

I tried below code, but failed to read the correct value from r11 following below reference of http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0472f/Cihfhjhg.html volatile int top_fp; __asm { mov top_fp, r11 } r11's value is 0x20009DCC top_fp's value is 0x00000004 [update] Solution, w...
bettermanlu
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99

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i2c transfer from gpio int handler fails on imx6sx cortex m4 side

i'm experiencing something that bugs me for days, so i am working on the imx6sx cortex m4 side, i have a sensor connected to one of the i2c buses, sensor is set up with data ready on INT1 which is connected to one of the gpios from the MCU. After boot, i configure the sensor so that it outputs data...
Mihai Pop
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1

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180

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error during cross-compilation of openvpn for arm-cortex uclinux

I am trying to cross compile openvpn using arm-uclinuxeabi toolchain getting error init.o: In function `do_persist_tuntap': init.c:(.text+0x1534): undefined reference to `tuncfg' error in following part of init.c #ifdef ENABLE_FEATURE_TUN_PERSIST tuncfg (options->dev, options->dev_type, options->de...
G.ONE
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1

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728

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Creating a loop within an assembly macro - IAR ARM

I am trying to create a loop within an IAR Arm assembly macro but cannot figure out how to make local labels, if the macro is called more than once I get duplicate label error from the assembler. My code is as follows: myMacro MACRO MOV R1, #0 label: enter code here do some stuff here ADD R1, R1, #...
Realtime Rik
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637

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Understanding the ctags file format

I used 'Exhuberant ctags' to index all the tags from my c-project. The c-project is embedded software for a Cortex-M7 microcontroller. The result is a tags-file. I'm trying to read this file and understand what is written down. Based on the documentation I find for ctags and Exhuberant ctags, I can...
K.Mulier
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2

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'Usage fault exception' in ARM Cortex M

I attended a lecture on FreeRtos and Cortex M where the instructor advised that if ISR safe version of API is not used from ISR it can lead to Usage fault exception in Cortex M processors.This would happen because this can involve going from interrupt context(interrupt handler) to task context(threa...
Furqan Qadri
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1

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79

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Assembler instructions and compilers

I wonder why different compilers use different assembly instructions. For instance I work with cc3200 from TI which has Cortex-M4 inside and here is a real piece of code from SDK: #if defined(ewarm) #define BACK_UP_ARM_REGISTERS() { \ __asm(' push {r0-r12,LR} \n' \ ' mov32 r1, vault_arm_...
Long Smith
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465

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How to use GCC LTO with differently optimized object files?

I'm compiling an executable with arm-none-eabi-gcc for a Cortex-M4 based microcontroller. Non-performance-critical code is compiled with -Os (optimized for executable code size) and performance critical parts with another optimalization flags, eg. -Og / -O2 etc. Is it safe to use -flto in such a bui...
Venemo
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1

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420

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How to link arm_cortexM4l_math.lib in Openstm32

I've included CMSIS_5 library, but I don't know how to link arm_cortexM4l_math.lib to my stm32 project for FFT. My board is stm32f407-DISCOVERY and I'm using Openstm32.
Jarosław Wieczorek
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tool to auto-correct addresses of manually modified disassembled assembly

I have an .obj and I disassemble it (I do not have the original source file). I modify the resulting assembly file by inserting my own assembly at certain instructions of interest, taking care to push/pop to the stack registers I use so I do not thrash the original content. Why? Maybe I want to togg...
Adrian
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322

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How do I configure MPU registers in cortex m4?

I want to add a protection to a region of a memory, starting from 0x20000000. The size of the region is 64 bytes. Permission is read only, no flag set except xn. Here's how I think it should be, #define MPU_CTRL (*((volatile unsigned long*) 0xE000ED94)) // MPU Control register #define MPU...
Muzahir Hussain
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2

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81

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STM3 USART+DMA not receiving

I've been learning how to program stm32's and I've come across an issue which I can't seem to debug on my own. Basically, I want to receive 3 bytes over UART and have them stored into memory using DMA. Any help would be greatly appreciated.The exact mode is the one on the nucleo-f401RE #include 'mai...
smokingRooster
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1

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0

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how to use gcc instrumentation options without a native filesystem

Many of the instrumentation options for gcc save data to a file during/after runtime: When the compiled program exits it saves this data to a file called auxname.gcda for each source file. However, I'm running on a custom C++-based RTOS which doesn't have a filesystem 'natively' like Linux. QUESTION...
Adrian
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2

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Changing priority of current interrupt in NVIC

I have a conundrum. The part I am using (NXP KL27, Cortex-M0+) has an errata in its I2C peripheral such that during receive there is no flow control. As a result, it needs to be a high priority interrupt. I am also using a UART that, by its asynchronous nature, has no flow control on its receive. As...
rjp
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MQX Lite LED task not work

I am using FRDM-KL25Z arm board from freescale and I have successfully Written LED blink program using code warrior IDE. I am also able to run all the sample program from freescale start up kit. Now I am writing A MQX Lite program to blink LED's using MQX tasks. I made three tasks One for Initialis...
Yogesh patel
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1

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4.1k

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Flash Memory writing and reading through SPI

It's the first time I try to use the SPI protocol. I am trying to understand an example code that came with my development kit (which has a STM32F207VCT6 microcontroller). This code implements communication (reading and writing) with a AT45DB041D flash memory. Every time this example code manages to...
Gui W. Eckert
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1

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158

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Fault on CortexM0+ From LDRH Instruction

I have a codebase that runs fine on the M3 architecture and am porting some code to the M0+. I am getting faults and I cannot figure out why. The exact micro I am on is the KL36Z128 (Freescale). I am using ARM-GCC-2013-Q3 release for my toolchain. So here is the C code (it's for parsing packets as t...
Brian Robertson
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1

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923

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STM32F4xx with GDB and OpenOCD bugs

I am developing a program on the STM32F4Discovery board using GCC, GDB and OpenOCD. I can compile everything just fine, but when I start debugging, the program goes straight to the HardFault Handler, instead of going to the Reset_Handler. Also, I frequently experience problems when writing to the fl...
user3416228
1

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2

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2.8k

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ERROR 65 in ARM KEIL 5 (Permissions error)

I'm relatively new in ARM Cortex M4 series micro-controller. When I'm trying to debug a simple project(blinky which easily just blinks a led on and off) using KEIL 5 simulator, I get an error like this: * error 65: access violation at 0x400FE608 : no 'read' permission * error 65: access violation at...
1

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2

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414

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Optimize C or assembly code in size for Cortex-M0

I need to reduce the code bloat for the Cortex-M0 microprocessor. At startup the ROM data has to be copied to the RAM data once. Therefore I have this piece of code: void __startup( void ){ extern unsigned int __data_init_start; extern unsigned int __data_start; extern unsigned int __data_end; // c...
ZxCvBnM

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