Questions tagged [cortex-m]

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Tiva ADC Sequencer with different step sources

I'm trying to measure some ADC channels with the same sequencer. I took a base on the Chapter 5 of Texas Tiva's ARM Cortex-M4 Workshop. So, my (interrupted) original code is working perfectly: #include #include #include 'inc/hw_memmap.h' #include 'inc/hw_types.h' #include 'inc/hw_ints.h' #include...
Rego
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Keil arm Cortex - Find middle number of 3

Lets say that i load 3 number values to three different registers. And i want to find the middle number. AREA median, CODE, READONLY EXPORT main first EQU 3 middle EQU 3 last EQU 9 ENTRY main MOV R0, #first MOV R1, #middle MOV R2, #last ---------- Here i would like to compare these 3 values and...
Ioan Kats
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STM32L0 Freeze on setting NVIC/GPIO

I'm working with an STM32L073RZ CPU running MbedOS 5.11.2. Eventually I aim to get this working in a very low-power mode (STOP mode) that will be awoken with either an RTC interrupt or an interrupt from a peripheral device on pin PA_0 (WAKEUP_PIN_1). At the moment I am simply attempting to setup PA_...
Adam Mitchell
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Is it a good embedded programming practice to disable an interrupt in an interrupt? [closed]

I want to implement something in an ARM Cortex-M3 processor (with NVIC). I have limited knowledge about embedded systems, but I know, that an ISR routine should be as simple as possible. Now I have the following problem: I have an interrupt routine which invokes when a CAN message is received. In on...
Zoltán Várnagy
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Cortex M0 vs M0+ Programming perspective

I am struggling with which cortex to choose. Currently I have a design guy that will give me an M0 with memory for initial development but I want to use M0+ eventually. Assuming I give up the optional features of the M0+ (MPU and MTB), can I transfer the M0 code to the M0+ without any changes? I mea...
DrorNohi
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ARM Cortex-M4 Interrupt priorities

I'm using an ARM Cortex M4 MCU. If I have an interrupt handler for a GPIO at priority 2 and an SPI driver at priority 3 (i.e., lower priority than the GPIO's), and I call a (blocking) SPI read from within the GPIO's interrupt handler, will the SPI function work?
tosa
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Is it possible to create a basic bare-metal Assembly bootup/startup program using only GNU LD command-line options

Is it possible to create a basic bare-metal Assembly bootup/startup program using only GNU LD command-line options in lieu of a customary -T scriptfile for a Cortex-M4 target? I have reviewed the GNU LD documentation and searched various locations including this site; however, I have not found any i...
InfinitelyManic
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CORTEX M4: Confusion on BX and BLX instruction and bit(0) of LR

My understanding is that for the cortex M4, the address register for BX and BLX must have bit(0) set to 1. I am confused how this works with regards to the BLX instruction, does the address inserted into the LR register after execution BLX instruction have bit(0) set to 1? Do I need to manually chan...
FourierFlux
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Fletchers algorithm in Assembly

On a discoboard (ARM7) I'm attempting to implement fletcher's algorithm from https://en.wikipedia.org/wiki/Fletcher%27s_checksum, and the input is a single 32 bit word. Couldn't implement the 32 bit version of fletcher's as it required loading a huge number into memory so: I'm splitting the 32 bit w...
Wboy
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Ineffective stack management and registers allocation

Consider the following code: extern unsigned int foo(char c, char **p, unsigned int *n); unsigned int test(const char *s, char **p, unsigned int *n) { unsigned int done = 0; while (*s) done += foo(*s++, p, n); return done; } Output in Assembly: 00000000 : 0: b5f8 push {r3, r4, r5, r6,...
Piotr Nowak
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How DAPLink make its virtual file system?

I am new to DAPLink. Just know that it could turn a cortex m0 chip into a mbed Interface, then we could program or debug thought it. But I found that the mbed Interface has about 8MB USB Disk. How does it work? As we known, a mbed Interface chip(such as 11u24) has only 8KB RAM and 64KB Flash.
JerryYip
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What does loadable mean in microcontrollers in the sense of linikers

I'm trying to get familiar with the linking and startup procedures in ARM Cortex-M4 microcontrollers. Looking through the linker scripts almost all the sections are marked as loadable. At first I thought that meant it would be copied from flash to RAM, but then I learned that doing that is handled i...
w1res
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Perform soft reset without losing RAM Data on ARM cortex M4

I am working on controller having architecture of ARM CORTEX M4. Flash of controller contains 2 different applications Boot loader and Application. I want allocated RAM section via to store some data which I will share in both boot loader and application. Problem for me is when I jump from one appl...
raj
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LPC4088 checksum value for Thumb?

In the LPC4088 user manual (p. 876) we can read that LPC4088 microcontroler has a really extraordinary startup procedure: This looks like a total nonsense and I need someone to help me clear things out... In the world of ARM I've heard countless times to put vector table looking like this: reset:...
71GA
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Data overriden when branch to PendSV

I have a little 'os' for an arm cortex m4. I implemented a wait function. But since then somehow, the context switch is corrupted. When stepping through the instructions i noticed, that for whatever reason the current_task variable gets overriden at entering the PendSV interrupt. These are global va...
R.S.
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How to trigger interrupts from a GPIO [closed]

I'm porting a toy app to the RTFM framework, and have a hard time figuring out how to trigger an interrupt via GPIO. fn init(p: init::Peripherals, _r: init::Resources) -> init::LateResources { let dp: stm32f103xx::Peripherals = p.device; let mut rcc = dp.RCC.constrain(); let mut gpioa = dp.GPIOA.spl...
Michael Böckling
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Avoiding CortexM Interrupt Nesting

I want to avoid nested interrupts at the interrupts entry in a CortexM based microcontroller. To achieve this I have an assembly file containing interrupt vectors and first instruction of each vector is the instruction (CPSID I) to disable interrupts globally. After every individual interrupt handle...
Rookie
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Are the PendSV / SVC exceptions raised immediately?

I'm working on a context saving and restoring mechanism on the Cortex-M4 so that I can implement simple multitasking. I use arm-none-eabi-g++ for compiling this code. Portability is not a concern for now. I use this for a form of cooperative multitasking when a task can call a yield function which w...
Venemo
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What is a good technique for accessing hardware registers in C++?

When using C on an embedded system one will often see something like this: #define PTA ((GPIO_Type *)PTA_BASE) Where GPIO_Type is a struct with volatile members. In a way this is like overlaying the data structure upon the memory mapped addresses. PTA_BASE will be a constant representing the base ad...
Kenny
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arm-none-eabi-ld malloc undefined reference

I'm working on some code for Texas Instruments' Tiva C Series TMC123G Launchpad (an ARM Cortex M4 MCU board), my code doesn't compile due to a undefined reference to 'malloc'. startup_gcc.c and project.ld are part of TivaWare. Equivalent files can be found here: /src/startup_gcc.c /TM4C123GH6PM.ld H...
Jakob Klepp
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stm32 JTAG pins using

I use SWD for load firmware in stm32 chip and debugging. It uses 3 pins: SWCLK(TCK), SWDIO(TMS) and GND. Can I use other JTAG pins, that not used in SWD interface: (TDI, TDO, TRST) for own purposes while preserving the possibility of flashing firmware in chip?
user3583807
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How can I program an ARM MCU using SWD under Linux?

I'm working with an STM32 ARM Cortex MCU. It supports a protocol called SWD (serial-wire debugging). Looking around on the web, I've found arm-none-eabi-gcc which seems to be a decent compiler, but on the hardware side I haven't really found a proper way to work with it. I haven't been able to find...
Venemo
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Double function indirection in C [duplicate]

This question already has an answer here: How do function pointers in C work? 12 answers I am writing a bootloader for an ARM Cortex-M0 CPU. I need to forward the IRQs to the target app, unfortunately the IRQ vector in this CPU is at fixed address and I cannot relocate it, so I need a bit of tricke...
Vitomakes
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Understanding cycle counts on Cortex M4

I'm playing around with an STM32F407 with a Cortex M4 and I'm measuring cycle counts of a function by reading DWT_CYCCNT directly before and after calling a function (in C) that I implemented in assembly. I'd like to understand the results that I get. 08000610 : 8000610: f04f 20ff mov.w...
Bla Blaat
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Reading peripheral register of Cortex M0 MCU using JLink and GDB

I'm trying to read the MCUs ADC register using GDB but I can't seem to find how it's done. Using x\10x 0x40012708 in gdb just returns zeroes, as do any memory mapped peripheral register I try to read. It this possible to do? If so, how is it done? Thanks!
evading
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VisualGDB doesnt create elf files

after buying the full version of VisualGDB i cannot find .elf files in new projects, and the old projects created with the TrialVersion wont open (unknown toolchain error). I need the .elf file for STMStudio, becouse the live variables are not so good in VisualGDB. After buying the key, VisualGDB d...
Michal D
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Using ARM DS-5 with Eclipse

I am trying to do some embedded programming for an online course. The IDE I had to use does not have a Linux version, so I am planning to use the ARM DS-5. It says it can be used with eclipse but I cannot figure out how to get them to work. I have Ubuntu 14.04. I read somewhere that the ARM-DS-5...
chamburger
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FRDM-KL25z assembly delay loop causes reset

I'm currently working on a project using the FRDM-KL25Z development board and programming using Keil MDK-lite (5.14a). What we're supposed to do is create a simple traffic light using three corresponding LEDs and a push button to expedite the light change(not immediately like a real traffic light bu...
ns533
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Can I port a library compliled for Cortex M3 onto a cortex M4?

I have received a library which is pre-compiled for cortex M3. Can I cross-compile it for cortex M4 and port it without access to the original source code?
VRTester
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STM32F4 FSMC/FMC SRAM as Heap/Stack results in random hardfaults

we are currently evaluating to use an external SRAM for C/C++ heap storage on our platform using a STM32F439BI microcontroller. The problem Using the SRAM as storage for heap results in random hardfaults which are raised from buserrors/imprecice buserrors. Without placing the heap on the SRAM, memor...
embeddedEngineer
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ARM interrupts from the beginning (Cortex-M4)

I am dealing with a new microcontroller LPC4088 from NXP. I needed 2 weeks to study and write a working examples for peripherals: IOCONFIG, GPIO, TIMERS, PWM and ADC. Please take a look at my repositories here. This is how you will get a feeling for how I work and what my skill level is. Until now...
71GA
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Are ARM Cortex-M0 Stacking Registers Saved On $psp or $msp During Hardfault?

I have an issue where my Cortex-M0 is hard faulting, so I am trying to debug it. I am trying to print the contents of the ARM core registers that were pushed to the stack when the hard fault occurred. Here is my basic assembly code: __attribute__((naked)) void HardFaultVector(void) { asm volatile( /...
eddie garcia
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CMSIS-RTOS Keil RTX - Proper way to enter ARM deep-sleep

Hello I would like to know what is the proper way to put ARM Cortex M0+ to deep sleep. Particularly I'm using CMSIS-RTOS RTX. The way my IRQ is handled is that ISR just set OS Signal and clear IRQ. Eg.: void ISR_A(){ osSignalSet(ID_Task_Handling_IRQ_A, IRQ_A_SIGNAL_CODE); DisableIRQ_A(); } Then in m...
Vit Bernatik
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ARM Cortex-R4F, Cache and MPU

On ARM Cortex-R4F, when I disable instruction and data cache using SCTLR register bits I and C, what happens to MPU region that defines region attribute as cachable (write-back)? Would it be ignored since global cache is disabled or would it result in unknown behavior?
Bill
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Ada on STM32F4 (Cortex-M4)

I just stumbled over this article stating that there exists a port of the Ada language to Cortex-M4 micro-processors. This seems exciting but unfortunately I have found no such indication on AdaCore. Our target would be a STM32F407 or STMF417 bare-metal. Real-Time extensions of Ada are of paramount...
Arne
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ARM Cortex M7 unaligned access and memcpy

I am compiling this code for a Cortex M7 using GCC: // copy manually void write_test_plain(uint8_t * ptr, uint32_t value) { *ptr++ = (u8)(value); *ptr++ = (u8)(value >> 8); *ptr++ = (u8)(value >> 16); *ptr++ = (u8)(value >> 24); } // copy using memcpy void write_test_memcpy(uint8_t * ptr, uint32_t...
Lou
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RTOS Datalogger example

I'm trying to develop a datalogger on a Cortex M0 (LPC11U14), and I was thinking of using a real-time OS like FreeRTOS, so that I can have one low-priority task that writes the data to SD, and multiple higher-priority timers that fetch the sensor data. Does anyone know of any code examples that can...
Muis
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IIR Lowpass filter using STM32F429 Discovery board in Keil uVision

I am designing an IIR 2nd order Lowpass filter with sampling frequency = 100Hz and cutoff frequency = 10 Hz. The filter coefficients are of Chebyshev Type I using fdatool in Matlab. But the code is not able to filter the signal (i.e. for all frequencies it gives the output with same amplitudes as th...
user11622
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How can I use crt0.o to setup .bss and .data in my bare metal C program?

I successfully wrote a bare metal C program which is running on my STM32F4. It's nothing fancy, just the usual led-blinky-program. In this project I have written the initialization routines which is clearing the .bss section and initializing the .data section myself. This wasn't really complicated....
Multisync
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C++ exception handler on gnu arm cortex m4 with freertos

Update 2016-12 There is now also a minimal example for this behavior: https://community.nxp.com/message/862676 I'm using a ARM Cortex M4 with freertos using freescales freedom Kinetis IDE (gnu arm toolchain). Problem is that try { throw 4; // old scenario also not working: throw std::runtime_error...
Superlokkus

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